photo
Mark Po-Hung Lin
Professor, Ph.D.
Department of Electrical Engineering
National Chung Cheng University
            Linkedin  
Address:
168 University Rd., Minxiong, Chiayi 621, Taiwan
Email:
marklin@ccu.edu.tw
Phone:
+886-5-2729310
Fax
+886-5-2720862
   Locations of 

Short Biography
Mark Po-Hung Lin received the B.S. and M.S. degrees in electronics engineering from National Chiao Tung University (NCTU), Hsinchu, Taiwan, and the Ph.D. degree in the Graduate Institute of Electronics Engineering, National Taiwan University (NTU), Taipei, Taiwan. He is currently a full professor in the Department of Electrical Engineering, National Chung Cheng University, Chiayi, Taiwan.

Dr. Lin has 7+ year industrial experience with SpringSoft, Inc. (acquired by Synopsys, Inc.), where he received the 2006 Best SpringSoft R&D Team Award as a technical manager and team leader. He co-initiated the "Laker Analog Prototyping" product with 5 patented technologies. He was also a Visiting Research Scholar with the University of Illinois at Urbana-Champaign, Champaign, IL, USA, during 20072009, a Humboldt Research Fellow with the Technical University of Munich (TUM), Germany, during 20132015, and a JSPS Invitation Fellow with Osaka University, Japan, in 2016. He has served in the technical program committees of premier VLSI design automation conferences, including ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design, Automation & Test in Europe (DATE), ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), and ACM International Symposium on Physical Design (ISPD). His research interests include design automation for analog/mixed-signal/RF integrated circuits and low-power resilient circuit and system design optimization.

Dr. Lin was the supervisor of two (out of three) 1st Place Award winners in 2017 ICCAD CAD Contest. He was also recipients of IEEE Best GOLD Member Award, Humboldt Research Fellowship for Experienced Researchers, JSPS Invitation Fellowship for Research in Japan, Distinguished Young Scholar Award of Taiwan IC Design Society, and Distinguished Young Faculty Award of National Chung Cheng University.

Research Interests
Computer-aided design and knowledge mining for analog/mixed-signal/RF IC
Low-power resilient circuit and system design optimization
Physical design for nanometer IC, FinFET, and new devices
Other interesting EDA problems for new process technologies and emerging applications

Honors & Awards
2017  Young Scholar Innovative Research Award, Taiwan Comprehensive University System (TCUS)
           106學年度 臺灣綜合大學系統 年輕學者創新研究選拔 優等獎 (第二次獲獎!!)

2017  IEEE Tainan Section Himax Award

2015  JSPS Invitation Fellowship for Research in Japan, Japan Socienty for the Promotion of Science (JSPS)


2015  Research Project for Outstanding Young Researchers, Ministry of Science and Technology (MOST)
           104學年度 科技部 優秀年輕學者研究計畫

2015  Carl Friedrich von Siemens Fellowship Supplement, Carl Friedrich von Siemens Foundation

2014  Best GOLD Member Award, IEEE Tainan Section


2014  Young Scholar Innovative Research Award, Taiwan Comprehensive University System (TCUS)
           103學年度 臺灣綜合大學系統 年輕學者創新研究選拔 優等獎


2014  Outstanding Young Electrical Engineer Award, Chinese Institute of Electrical Engineering
           103 學年度 中國電機工程學會 優秀青年電機工程師獎



2014  Distinguished Young Scholar Award, Taiwan IC Design Society
           103學年度 臺灣積體電路設計學會 傑出年輕學者獎
2013  Macronix Award, IEEE Tainan Section
2013  Humboldt Research Fellowship for Experienced Researchers, Alexander von Humboldt (AvH) Foundation



2013  Distinguished Young Faculty Award, National Chung Cheng University
           101學年度 國立中正大學 青年學者獎


2013  Distinguished Young Faculty Award, College of Engineering, National Chung Cheng University
           101學年度 國立中正大學工學院 青年學者獎

2006  Best Annual R&D Team Award, Springsoft, Inc.


Exellence in Supervision
The 1st Place Award of 2017 ICCAD CAD Contest (Problem A: Resource-aware Patch Generation)
The 1st Place Award of 2017 ICCAD CAD Contest (Problem B: Net Open Location Finder with Obstacles)


2017 Synopsys APPs Design Contest「佳作」
2017 國際積體電路電腦輔助設計軟體製作競賽 電題組國內賽「優等」(E組)

2017 全國大專院校產學創新實作競賽 資訊電子組「第二名」

2017 IEEE Tainan Section Best Master Thesis Award



The 1st Place Award of 2016 ICCAD CAD Contest (Problem A: Identical Fault Search)
中正大 學焦點新聞



2016 Synopsys APPs Design Contest「佳作」
中正電 機系榮譽榜
2016 國際積體電路電腦輔助設計軟體製作競賽 電題組國內賽「優等」(E組)
2015 中華民國資訊學會碩士最佳論文獎「佳作」兩件
2015 中國電機工程學會 青年論文獎「第三名」
2015 Synopsys APPs Design Contest「優等」及「佳作」各一件
2015 TIEEE 最佳博士論文獎「佳作」


The 1st Prize of the Master Thesis Award, Institute of Information & Computing Machinery (IICM), 2014
2014 中華民國資訊學會碩士最佳論文獎「優等獎」
2014 Synopsys APPs Design Contest「佳作」
2014 傑出人才發展基金會「優秀學生出國開會補助」
Best Paper Award in 2014 IEEE International Symposium on Bioelectronics and Bioinformatics (ISBB-2014)



The 3rd Prize of the Best Paper Award, Biomedical Engineering Symposium on Biosignal, Biosensor, Bioelectronics, and Bioengineering, 2013
102 學年度醫療電子聯盟4B生醫工程研討會「佳作論文獎」

2013 傑出人才發展基金會「優秀學生出國開會補助」
2013 TIEEE 最佳碩士論文獎「佳作」

2013 Synopsys APPs Design Contest「優等」
102 學年度中國工程師學會學生工程論文競賽「佳作」
101 學年度台灣積體電路設計學會(TICD)「碩士論文獎」
2012 SpringSoft APPs Design Contest「佳作」
100 學年度台灣積體電路設計學會(TICD)「碩士論文獎」
99 學年度大專校院積體電路電腦輔助設計(CAD)軟體製作競賽「佳作」

2010 東元科技綠能技術(Green Tech)創意競賽「佳作」
2010 思源EDA獎勵金

98 學年度大專校院積體電路電腦輔助設計(CAD)軟體製作競賽「優等」(B組)

Professional Societies
Senior Member  Institute of Electrical and Electronics Engineers (IEEE)
Life Member Association of Computing Machinery (ACM)
Life Member
Taiwan IC Design Society (TICD)
Life Member
Institute of Information & Computing Machinery (IICM)
Life Member Chinese Institute of Electrical Engineering (CIEE)
Life Member Taiwan Institute of Electrical and Electronic Engineering (TIEEE)

Professional Activities
Chair
Contest Chair of 2018 ICCAD CAD Contest
General Chair of 2018 IEEE/ACM International Seasonal School on Physical Design Automation
Chair of ACM SIGDA Taiwan Chapter, 2016--2017

Guest Editor
Integration, the VLSI Journal, 2015

Organizer & Co-organizer
Special Session, IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), 2015
International Workshop on Design Automation for Analog and Mixed-Signal Circuits, co-located with ICCAD, 2014

CAD Contest (馬拉松組), Taiwan, 2014--2015

EDA Forums, Taiwan, 2011--2012


Technical Program Committee Member
ACM/IEEE Design Automation Conference (DAC), 2016--2018
ACM/IEEE Design, Automation & Test in Europe (DATE), 2016--2018
ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), 2014--2016, 2018
ACM/IEEE International Conference on VLSI Design (VLSID), 2016--2018
ACM International Symposium on Physical Design (ISPD), 2016--2018
IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD), 2012, 2015--2017
ACM SIGDA Ph.D. Forum @ DAC, 2015
Frontiers in Analog CAD (FAC), International Workshop on Design Automation for Analog and Mixed-Signal Circuits, co-located with ICCAD, 2015
Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI), 2012--2013
Workshop on Computer Architecture, Embedded Systems, SoC, and VLSI/EDA, International Computer Symposium (ICS), 2014
VLSI Design/CAD Symposium, 2012, 2015--2017

Award Committee Member
Best Paper Award of IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), 2016
Outstanding Dissertation Award of European Design and Automation Association (EDAA), 2014--2015
Best Paper Award of International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD), 2012
Best Paper Award of VLSI Design/CAD Symposium, 2016

Session
Chair
ACM/IEEE Design Automation Conference (DAC), 2014
ACM/IEEE Design, Automation & Test in Europe (DATE), 2017
IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), 2014, 2015, 2016
IEEE International Symposium on Bioelectronics and Bioinformatics (ISBB), 2014
IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD), 2012
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2012
IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT), 2011
Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI), 2015
VLSI Design/CAD Symposium, Taiwan, 2011, 2014

Reviewer
ACM Transactions on Design Automation on Electronic Systems (ACM TODAES)
ACM Journal on Emerging Technologies in Computing Systems (ACM JETC)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD)
IEEE Transactions on Circuits and Systems I (IEEE TCAS-I)
IEEE Transactions on Circuits and Systems II (IEEE TCAS-II)
IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI)
IEICE Electronics Express
International Journal of Electrical Engineering (IJEE)
Integration the VLSI Journal
ACM/IEEE Design Automation Conference (DAC)
ACM/IEEE Design, Automation & Test in Europe (DATE)
IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC)
IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design (SMACD)
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)
IEEE International Symposium on Circuits and Systems (ISCAS)
IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT)
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
International Computer Symposium -- Workshop on Computer Architecture, Embedded Systems, SoC, and VLSI/EDA
Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI)
VLSI Design/CAD Symposium

Invited Talks/
Tutorials
IEEE CASS Seasonal School on Physical Design Automation, UFRGS, Brazil, August 2017
Tunghai University, Taiwan, March 2017
National Chi Nan University (NCNU), Taiwan, October 2016
Taiwan and Japan Conference on Circuits and Systems (TJCAS), July 2016
Yuan Ze University (YZU), Taiwan, July 2016
National Chiao Tung University (NCTU), Taiwan, April 2016
Tsinghua University, China, April 2016
Tunghai University, Taiwan, March 2016
Tokyo Institute of Technology (Tokyo Tech), Japan, February 2016
Osaka University, Japan, February 2016
Kyoto University, Japan, February 2016
University of Kitakyushu, Japan, February 2016
Yuan Ze University (YZU), Taiwan, December 2015
IBM T. J. Watson Research Center, USA, November 2015
National Cheng Kung University (NCKU), Taiwan, October 2015
Tsinghua University, China, September 2015
Peking University, China, September 2015
Karlsruhe Institute of Technology (KIT), Germany, August 2015
Robert Bosch Center for Power Electronics (rbz), Germany, July 2015
Technical University of Munich (TUM), Germany, August 2014
National Tsing Hua University (NTHU), Taiwan, May 2014
Technical University of Munich (TUM), Germany, January 2014
National Sun-Yat-Sen University (NSYSU), Taiwan, March 2011
Yuan Ze University (YZU), Taiwan, March 2010
National Central University (NCU), Taiwan, January 2010
National Cheng Kung University (NCKU), Taiwan, December 2009
University of Illinois at Urbana-Champaign (UIUC), CA, April 2008
Waseda University, Japan, January 2007

Publications
Journal Papers
  1. A. Q. Dao, M. P.-H. Lin, and A. Mishchenko, "SAT-based fault equivalence checking in functional safety verification," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), to be published. (Top Journal in EDA Field)

  2. M. P.-H. Lin, V. W.-H. Hsiao, C.-Y. Lin, and N.-C. Chen, "Parasitic-aware common-centroid binary-weighted capacitor layout generation integrating placement, routing, and unit capacitor sizing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 36, No. 8 pp. 1274--1286, August 2017. (Top Journal in EDA Field)

  3. T.-M. Tseng, B. Li, C.-F. Yeh, H.-C. Jhan, Z.-M. Tsai, M. P.-H. Lin, and U. Schlichtmann, "An efficient two-phase ILP-based algorithm for precise CMOS RFIC layout generation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 36, No. 8 pp. 1313--1326, August 2017. (Top Journal in EDA Field)

  4. P.-Y. Chou, N.-C. Chen, M. P.-H. Lin, and H. Graeb, "Matched-routing common-centroid 3-D MOM capacitors for low-power data converters," IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI), Vol. 25, No. 8 pp. 2234--2247, August 2017.

  5. C.-C. Hsu, M. Hashimoto, and M. P.-H. Lin, "Minimizing detection-to-boosting latency toward low-power error-resilient circuits," Integration, the VLSI Journal, Vol. 58, pp. 236--244, June 2017.

  6. M. P.-H. Lin, P.-H. Chang, S.-Y. Lee, and H. E. Graeb, "DeMixGen: Deterministic mixed-signal layout generation with separated analog and digital signal paths," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 35, No. 8, pp. 1229--1242, August 2016. (Top Journal in EDA Field)

  7. P.-H. Wu, M. P.-H. Lin, X. Li, and T.-Y. Ho, "Parasitic-aware common-centroid FinFET placement and routing for current-ratio matching," ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), Vol. 21, No. 3, pp. 39:1--39:22, July 2016.

  8. M. P.-H. Lin, C.-C. Hsu, and Y.-C. Chen, "Clock-tree aware multi-bit flip-flop generation during placement for power optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 34, No. 2, pp. 280--292, February 2015. (Top Journal in EDA Field)

  9. P.-H. Wu, M. P.-H. Lin, T.-C. Chen, C.-F. Yeh, X. Li, and T.-Y. Ho, "A novel analog physical synthesis methodology integrating existent design expertise," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 34, No. 2, pp. 199--212, February 2015. (Top Journal in EDA Field)

  10. C.-C. Hsu, M. P.-H. Lin, and Y.-T. Chang, "Crosstalk-aware multi-bit flip-flop generation for power optimization," Integration, the VLSI Journal, Vol. 48, pp. 146--157, January 2015.

  11. P.-H. Wu, M. P.-H. Lin, T.-C. Chen, C.-F. Yeh, T.-Y. Ho, and B.-D. Liu, "Exploring feasibilities of symmetry islands and monotonic current paths in slicing trees for analog placement," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 33, No. 6, pp. 879--892, June 2014. (Top Journal in EDA Field)
  12. M. P.-H. Lin, Y.-T. He, V. W.-H. Hsiao, R.-G. Chang, and S.-Y. Lee, "Common-centroid capacitor layout generation considering device matching and parasitic minimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 32, No. 7, pp. 991--1002, July 2013. (Top Journal in EDA Field)

  13. P.-H. Wu, M. P.-H. Lin, T.-C. Chen, T.-Y. Ho, Y.-C. Chen, S.-R. Siao, and S.-H. Lin, "1-D cell generation with printability enhancement," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 32, No. 3, pp. 419--432, March 2013. (Top Journal in EDA Field)

  14. M. P.-H. Lin, C.-C. Hsu, and Y.-T. Chang, "Post-placement power optimization with multi-bit flip-flops," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 30, No. 12, pp. 1870--1882, December 2011. (Top Journal in EDA Field)

  15. M. P.-H. Lin, H. Zhang, M. D. F. Wong, and Y.-W. Chang, "Thermal-driven analog placement considering device matching," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 30, No. 3, pp. 325--336, March 2011. (Top Journal in EDA Field)

  16. S.-Y. Lee, C.-Y. Chen, J.-H. Hong, R.-G. Chang, and M. P.-H. Lin, "Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist," Microelectronics Journal (MEJ), Vol. 42, Issue 2, pp. 347--357, February 2011.

  17. P.-H. Lin, Y.-W. Chang, and S.-C. Lin, "Analog placement based on symmetry-island formulation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 28, No. 6, pp. 791--804, June 2009. (Top Journal in EDA Field)

Book Chapters
  1. R. A. Rutenbar, J. M. Cohn, M. P.-H. Lin, and F. Baskaya, "Layout tools for analog integrated circuits and mixed-signal system-on-chip: A survey," EDA for IC Implementation, Circuit Design, and Process Technology (Electronic Design Automation for Integrated Circuits Handbook), CRC Press, 2nd Ed., pp. 479--499, April 2016.

  2. M. P.-H. Lin and Y.-W. Chang, "Hierarchical placement with layout constraint," Analog Layout Synthesis: A Survey of Topological Approaches (Helmut E. Graeb, Editor), Springer, pp. 61--94, October 2010. (ISBN-10: 1441969314; ISBN-13: 978-1441969316)

International Conference Papers (with Proceedings)
  1. G.-G. Fan and M. P.-H. Lin, "State retention for power-gated circuits with non-uniform multi-bit retention latches," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2017), Urvine, CA, November 2017. (Top Conference in EDA Field)

  2. H. Liu, Z. Liu, F. Qiao, M. P.-H. Lin, Q. Wei, H. Yang, "AIsim: Functional simulator for analog-to-information perception systems," in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2017), Bochum, Germany, July 2017.

  3. N.-C. Chen, P.-Y. Chou, H. Graeb, and M. P.-H. Lin, "High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADCs," in Proceedings of ACM/IEEE Design, Automation & Test in Europe (DATE-2017), Lausanne, Switzerland, March 2017.

  4. T.-M. Tseng, B. Li, C.-F. Yeh, H.-C. Jhan, Z.-M. Tsai, M. P.-H. Lin, and U. Schlichtmann, "Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2016), Austin, TX, June 2016. (Top Conference in EDA Field)

  5. C.-C. Hsu, M. P.-H. Lin, and M. Hashimoto, "Latch clustering for minimizing detection-to-boosting latency toward low-power resilient circuits," in Proceedings of ACM/IEEE International Workshop  on System Level Interconnect Prediction (SLIP-2016), Austin, TX, June 2016.

  6. P.-Y. Chou, M. P.-H. Lin, and H. Graeb, "An integrated placement and routing for ratioed capacitor array based on ILP formulation," in Proceedings of IEEE International Symposium on VLSI Design Automation and Test (VLSI-DAT-2016), Hsinchu, Taiwan, April 2016.

  7. M. P.-H. Lin, Y.-W. Chang, and C.-M. Hung, "Recent research development and new challenges in analog layout synthesis," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2016), pp. 617--622, Macao, January 2016. (Invited Special Session Paper)

  8. P.-H. Wu, M. P.-H. Lin, and T.-Y. Ho, "Analog layout synthesis with knowledge mining," in Proceedings of IEEE European Conference on Circuit Theory and Design (ECCTD-2015), Trondheim, Norway, August 2015.

  9. Y.-C. Chen, C.-C. Hsu, and M. P.-H. Lin, "Low-power gated clock tree optimization for three-dimensional integrated circuits," in Proceedings of IEEE International Symposium on VLSI Design Automation and Test (VLSI-DAT-2015), Hsinchu, Taiwan, April 2015.

  10. P.-H. Wu, M. P.-H. Lin, X. Li, and T.-Y. Ho, "Common-centroid FinFET placement considering the impact of gate misalignment," in Proceedings of ACM International Symposium on Physical Design (ISPD-2015), pp. 25--31, Monterey, CA, March 2015.

  11. S.-H. Lin and M. P.-H. Lin, "More effective power-gated circuit optimization with multi-bit retention registers," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2014), pp. 213--217, San Jose, CA, November 2014. (Top Conference in EDA Field)

  12. M. P.-H. Lin, V. W.-H. Hsiao, and C.-Y. Lin, "Parasitic-aware sizing and detailed routing for binary-weighted capacitors in charge-scaling DAC," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2014), San Francisco, CA, June 2014. (Top Conference in EDA Field)

  13. S-R. Siao, C.-C. Hsu, M. P.-H. Lin, and S.-Y. Lee, "A Novel approach for ECG data compression in healthcare monitoring system," in Proceedings of IEEE International Symposium on Bioelectronics and Bioinformatics (ISBB-2014), Taoyuan, Taiwan, April 2014. (Best Paper Award)

  14. S.-Y. Chang Chien, M. P.-H. Lin,  Q. Fang, and S-Y. Lee, "Implementation of a real-time ECG signal processor," in Proceedings of IEEE International Symposium on Bioelectronics and Bioinformatics (ISBB-2014), Taoyuan, Taiwan, April 2014.

  15. S.-C. Lo, C.-C. Hsu, and M. P.-H. Lin, "Power optimization for clock network with clock gate cloning and flip-flop merging," in Proceedings of ACM International Symposium on Physical Design (ISPD-2014), pp. 77--83, Petaluma, CA, March 2014.

  16. C.-C. Hsu, Y.-C. Chen, and M. P.-H. Lin, "In-placement clock-tree aware multi-bit flip-flop generation for power optimization," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2013), pp. 592--598, San Jose, CA, November 2013. (Top Conference in EDA Field)

  17. P.-H. Wu, M. P.-H. Lin, T.-Y. Ho, and Y.-C. Chen, "Lithography-aware 1-dimensional cell generation," in Proceedings of European Conference on Circuit Theory and Design (ECCTD-2013), Dresden, Germany, September 2013.
  18. P.-H. Wu, M. P.-H. Lin, Y.-R. Chen, B.-S. Chou, T.-C. Chen, T.-Y. Ho, and B. D. Liu, "Performance-driven analog placement considering monotonic current paths," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2012), pp. 613--619, San Jose, CA, November 2012. (Top Conference in EDA Field)

  19. V. W.-H. Hsiao, Y.-T. He, M. P.-H. Lin, R.-G. Chang, and S.-Y. Lee, "Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC," in Proceedings of IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD-2012), pp. 173--176, Seville, Spain, September 2012.

  20. M. P.-H. Lin, B.-H. Chiang, J.-C. Chang, Y.-C. Wu, R.-G. Chang, and S.-Y. Lee, "Augmenting slicing trees for analog placement," in Proceedings of IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD-2012), pp. 57--60, Seville, Spain, September 2012.

  21. C.-C. Hsu, Y.-T. Chang, and M. P.-H. Lin, "Crosstalk-aware power optimization with multi-bit flip-flops," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2012), pp. 431--436, Sidney, Australia, January 2012.

  22. H.-F. Tsao, P.-Y. Chou, S.-L. Huang, Y.-W. Chang, M. P.-H. Lin, D.-P. Chen, and D. Liu, "A corner stitching compliant B-tree representation and its applications to analog placement," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2011), pp. 507--511, San Jose, CA, November 2011. (Top Conference in EDA Field)

  23. M. P.-H. Lin, "Recent research in analog placement considering thermal gradient," in Proceedings of IEEE European Conference on Circuit Theory and Design (ECCTD-2011), pp. 358--361, Linkoping, Sweden, August 2011. (Invited Special Session Paper)

  24. M. P.-H. Lin, C.-C. Hsu, and Y.-T. Chang, "Recent research in clock power saving with multi-bit flip-flops," in Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS-2011), Seoul, Korea, August 2011. (Invited Special Session Paper)

  25. Y.-T. Chang, C.-C. Hsu, M. P.-H. Lin, Y.-W. Tsai, and S.-F. Chen, "Post-placement power optimization with multi-bit flip-flops," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2010), pp. 218--223, San Jose, CA, November 2010. (Top Conference in EDA Field)

  26. P.-H. Lin, H. Zhang, M. D. F. Wong, and Y.-W. Chang, "Thermal-driven analog placement considering device matching," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2009), pp. 593--598, San Francisco, CA, July 2009. (Top Conference in EDA Field)

  27. H. Graeb, F. Balasa, R. Castro-Lopez, Y.-W. Chang, F. V. Fernandez, P.-H. Lin, and M. Strasser, "Analog layout synthesis - Recent advances in topological approaches,'' in Proceedings of ACM/IEEE Design, Automation & Test in Europe (DATE-2009), pp. 274--279, Nice, France, April 2009. (Invited Special Session Paper)

  28. P.-H. Lin and S.-C. Lin, "Analog placement based on hierarchical module clustering," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2008), pp. 50--55, Anaheim, CA, June 2008. (Top Conference in EDA Field)

  29. P.-H. Lin and S.-C. Lin, "Analog placement based on novel symmetry-island formulation," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2007), pp. 465--470, San Diego, CA, June 2007. (Top Conference in EDA Field)

  30. P.-H. Lin, H.-C. Yu, T.-H. Tsai, and S.-C. Lin, "A matching-based placement and routing system for analog design," in Proceedings of IEEE International Symposium on VLSI Design Automation and Test (VLSI-DAT-2007), pp. 16--19, Hsinchu, Taiwan, April 2007. (Invited Industrial Session Paper)

U.S. Patents
  1. T.-C. Chen, P.-H. Wu, P.-H. Lin, and T.-Y. Ho, "Knowledge-based analog layout generator," U.S. Patent 9,256,706, February 9 2016.

  2. P.-H. Lin, Y.-Y. He, and W.-H. Hsiao, "Method of common-centroid IC layout generation," U.S. Patent 8,751,995, June 10, 2014.

  3. P.-H. Lin, "Analog IC placement using symmetry-islands," U.S. Patent 7,877,718, January 25, 2011.

  4. P.-H. Lin, W.-C. Chao, and S.-C. Lin, "Hierarchical analog IC placement subject to symmetry, matching, and proximity constraints," U.S. Patent 7,873,928, January 18, 2011.

  5. P.-H. Lin, H.-C. Yu, T.-H. Tsai, S.-C. Lin, and S.-H. Bai, "Analog and mixed-signal IC layout system,'' U.S. Patent 7,739,646, June 15, 2010.

  6. T.-H. Tsai, P.-H. Lin, S.-C. Lin, and H.-C. Yu, "Rule-based schematic diagram generator," U.S. Patent 7,386,823, June 10, 2008.

  7. P.-H. Lin and S.-C. Lin, "Schematic diagram generation and display system," U.S. Patent 7,178,123, February 13, 2007.

Other Conference / Symposium / Workshop Papers or Posters (without Proceedings)
  1. Y.-C. Chen, C.-C. Hsu, and M. P.-H. Lin, "Low-power gated clock tree synthesis for 3D ICs," the 19th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Ilan, Taiwan, March 2015.

  2. M. P.-H. Lin, Y.-T. He, V. W.-H. Hsiao, and C.-Y. Lin, "Parasitic-aware capacitor sizing and layout generation for binary-weighted capacitors in charge-scaling DAC," the 25th VLSI Design/CAD Symposium, Taichung, Taiwan, August 2014.

  3. C.-C. Hsu, Y.-C. Chen, M. P-H. Lin, "A new paradigm for power optimization with multi-bit flip-flops," the 25th VLSI Design/CAD Symposium, Taichung, Taiwan, August 2014.

  4. P.-H. Wu, M. P.-H. Lin, T.-C. Chen, C.-F. Yeh, T.-Y. Ho, and B.-D. Liu, "Analog placement considering monotonic current paths," the 25th VLSI Design/CAD Symposium, Taichung, Taiwan, August 2014.

  5. S.-R. Siao, M. P.-H. Lin, and S.-Y. Lee, "More effective ECG data compression for low-power wireless communication," Biomedical Engineering Symposium on Biosignal, Biosensor, Bioelectronics, and Bioengineering, Taoyuan, Taiwan, January 2014. (佳作論文獎)

  6. P.-H. Wu, T.-Y. Ho, C.-F. Yeh, M. P.-H. Lin, and T.-C. Chen, "Analog placement considering monotonic current/signal flows," International Workshop on Design Automation for Analog and Mixed-Signal Circuits, San Jose, November 2013.

  7. C.-C. Hsu, Y.-T. Chang, and M. P.-H. Lin, "Flip-flop clustering for power saving with crosstalk constraints," the 23th VLSI Design/CAD Symposium, Pingtung, Taiwan, August 2012.

Thesis / Dissertation
  1. P.-H. Lin, Hierarchical Analog Circuit Placement, Ph.D. dissertation, National Taiwan University.

  2. P.-H. Lin, Analysis and Design of a Shared-memory Interface for SoC Applications, M.S. thesis, National Chiao Tung University.